High frequency power amplifier module and wireless communication apparatus

ABSTRACT

The number of components of a high frequency power amplifier is reduced. A bias resistance ratio is adjusted in accordance with a change in the threshold voltage Vth of a transistor. There is provided a high frequency power amplifier having a plurality of amplifying systems, characterized in that each of the amplifying systems comprises an input terminal to which a signal to be amplified is supplied, an output terminal,  
     a bias terminal, a plurality of amplifying stages which are sequentially cascaded between the input terminal and output terminal, and a bias circuit connected to the bias terminal and each of the amplifying stages to apply a bias potential to the amplifying stage, in that the amplifying stage includes a control terminal for receiving an input signal and the bias potential supplied to the stage and a first terminal for transmitting an output signal of the stage, and in that a first amplifying stage and a second amplifying stage of each of the amplifying systems are monolithically formed on a single semiconductor chip, and a part of bias resistors that constitute bias circuits of the first amplifying stage and second amplifying stage are monolithically formed on the semiconductor chip.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a high frequency power amplifierhaving a pluralty of amplifying systems and a wireless communicationapparatus including the high frequency power amplifier, and particularlyrelates to a technology usefully applicable to a multi-bandcommunication type of cellular phone which has multiple communicationfunctions of different communication frequencies.

[0003] 2. Prior Art

[0004] In North American cellular phone market, so-called dual modecellular phones have recently been spreading which are cellular phonesincorporating conventional analog AMPS (advanced mobile phone services)that cover the whole of the North America and digital services such asTDMA (time division multiple access) and CDMA (code division multipleaccess).

[0005] In other regions including Europe, GSM (Global system for mobilecommunication and DCS (digital cellular system) utilizing TDMAtechniques and FDD (frequency division duplex) techniques are used.

[0006] In “Nikkei Electronics” pp. 140-153 published by Nikkei BP Corp.on Jul. 26, 1999 [No. 748], a dual mode cellular phone was disclosed inwhich a GSM having an operating frequency of 800 to 900 MHz and a DCShaving an operating frequency of 1.7 to 1.8 GHz are integrated. The samearticle disclosed a multi-layer ceramics device in which passivecomponents are integrated to make the circuit as a whole compact.

[0007] Further, a dual band RF power module was disclosed in “GAIN” No.131, January 2000 published by Semiconductor Group of Hitachi, Ltd.

SUMMARY OF THE INVENTION

[0008] There is a trend toward cellular phones with increased functionsto allow advanced information communication. High frequency poweramplifiers (high frequency power amplifier modules) incorporated incellular phones have more functions to satisfy such a need. Especially,high frequency power amplifiers having a plurality of communicationmodes (and communication bands) are assembled from a greater number ofcomponents compared to single communication mode products, whichincreases the size and cost of such devices.

[0009] Under such circumstances, the inventors studied the possibilityof a reduction in the number of chip resistors incorporated in a highfrequency power amplifier in order to provide the amplifier with smalleroutline dimensions.

[0010]FIG. 23 is a circuit diagram showing the relationship between anequivalent circuit of a conventional dual band type high frequency poweramplifier module incorporating a GSM and a DCS and semiconductor chipsand the like. The high frequency power amplifier module has anamplifying system e for GSM as a first amplifying system and anamplifying system f for DCS as a second amplifying system.

[0011] The GSM amplifying system e has a three-stage consistingconfiguration (consisting of a first amplifying stage, a secondamplifying stage, and a third amplifying stage (final amplifying stage))in which transistors Q1, Q2, and Q3 are sequentially cascaded between aninput terminal Pin-GSM and an output terminal Pout-GSM.

[0012] Each of the transistors Q1, Q2 and Q3 is constituted by a MOSFET(metal oxide semiconductor field-effect-transistors) and is applied witha signal and a bias potential at its gate electrode which is a controlterminal. The bias potential is applied to a bias terminal Vapc-GSM (orautomatic power control terminal), and a predetermined bias potential isapplied to the respective control terminal through bias resistors R1through R5.

[0013] A power supply potential Vdd-GSM is applied to a first terminal(drain terminal) of each of the transistors Q1, Q2, and Q3, and anamplification signal is output to the first terminal. A referencepotential (ground potential) is supplied to a second terminal (sourceelectrode) of the transistors. L1 through L7 represent a matchingcircuit.

[0014] The DCS amplifying system f has the same configuration as that ofthe above-described GSM amplifying system e. Specifically, it has athree-stage configuration (consisting of a first amplifying stage, asecond amplifying stage, and a third amplifying stage (final amplifyingstage)) in which transistors Q4, Q5, and Q6 are sequentially cascadedbetween an input terminal Pin-DCS and an out put terminal Pout-DCS.

[0015] Each of the transistors Q4, Q5 and Q6 is constituted by a MOSFETand is applied with a signal and a bias potential at its gate electrodewhich is a control terminal. The bias potential is applied to a biasterminal Vapc-DCS, and a predetermined bias potential is applied to therespective control terminal through bias resistors R6 through R10.

[0016] A power supply potential Vdd-DCS is applied to a first terminal(drain terminal) of each of the transistors Q4, Q5, and Q6, and anamplification signal is output to the first terminal. A referencepotential (ground potential) is supplied to a second terminal (sourceelectrode) of the transistors. L8 through L14 represent a matchingcircuit.

[0017] The transistors Q1 and Q2 of the GSM amplifying system e and DCSamplifying system f have a monolithic configuration in that they areincorporated in a single semiconductor chip. In such a configuration,however, bias resistors are externally mounted, which hinders reductionof the size of high frequency power amplifiers. Further, while the firstand second amplifying stages of both the GSM amplifying system e and DCSamplifying system f are integrated in one semiconductor chip, twosemiconductor chips are required because there are two amplifyingsystems, which also hinders reduction of the size of high frequencypower amplifiers.

[0018] Referring to the transistors that constitute the amplifyingstage, since the threshold voltage Vth of the transistors is slightlyinconsistent (varies) between production lots, the bias resistanceratios of the resistors that form a bias circuit must be changed fromlot to lot. This method makes manufacturing operations complicatedbecause chip resistors must be selected for use in each production lot.

[0019] It is an object of the invention to provide a compact highfrequency power amplifier and a wireless communication apparatusincorporating the same high frequency power amplifier.

[0020] It is another object of the invention to provide a technique forallowing a bias resistance ratio to be easily adjusted in accordancewith a change in a threshold voltage Vth of a transistor.

[0021] The above and other objects and novel features of the inventionwill become apparent from the description of the present specificationand the accompanying drawings.

[0022] Briefly, primary aspects of the invention disclosed in thisspecification are as follows.

[0023] (1) There is provided a high frequency power

[0024] amplifier having a plurality of amplifying systems, characterizedin that each of the amplifying systems comprises:

[0025] an input terminal to which a signal to be amplified is supplied;

[0026] an output terminal;

[0027] a bias terminal;

[0028] a plurality of amplifying stages which are sequentially cascadedbetween the input terminal and output terminal; and

[0029] a bias circuit connected to the bias terminal and each of theamplifying stages to apply a bias potential to the amplifying stage, inthat each of the amplifying stages includes a control terminal forreceiving an input signal and the bias potential supplied to the stageand a first terminal for transmitting an output signal of the stage, andin that a first amplifying stage and a second amplifying stage of eachof the amplifying systems are monolithically formed on a singlesemiconductor chip, and a part of bias resistors that constitute biascircuits of the first amplifying stage and second amplifying stage aremonolithically formed on the semiconductor chip.

[0030] Referring to the terminals of the first amplifying stage andsecond amplifying stage provided on a surface of the semiconductor chip,the control terminals and the first terminals are alternately providedin the same direction.

[0031] A wire that is connected to the control terminal of the secondamplifying stage provided on the surface of the semiconductor chip and awire connected to the first terminal of the second amplifying stageextend in directions orthogonal to each other or in directions crossingeach other.

[0032] The bias resistance ratio of the first amplifying stage of eachof the amplifying systems or the bias resistance ratios of the firstamplifying stage and second amplifying stage can be adjusted.Specifically, the bias resistance ratio of the first amplifying stage orthe bias resistance ratios of the first amplifying stage and secondamplifying stage are adjusted by selecting connecting positions ofelectrical connectors that connect the plurality of bias resistorsformed on the surface of the semiconductor chip, the choice including noconnection with the electrical connectors.

[0033] Such a high frequency power amplifier is incorporated in awireless communication apparatus to allow dual band communication.

[0034] With the means as described in the above (1), (a) since the firstamplifying stage and second amplifying stage of each amplifying systemare monolithically formed on a single semiconductor chip, a compact sizecan be achieve compared to a structure in which they are incorporated inseparate semiconductor chips. Since a part of bias resistors thatconstitute bias circuits for the first amplifying stage and secondamplifying stage are monolithically formed on the semiconductor chip,the high frequency power amplifier can be made compact compared to astructure in which chip resistors are separately mounted.

[0035] (b) The size and manufacturing cost of the high frequency poweramplifier can be reduced through a reduction in the number of componentsthat is achieved by monolithically forming the first amplifying stageand second amplifying stage of each amplifying system on a singlesemiconductor chip and by monolithically forming a part of biasresistors that constitute bias circuits for the first amplifying stageand second amplifying stage on the semiconductor chip as described inthe above (1).

[0036] (c) Referring to the terminals of the first amplifying stage andsecond amplifying stage provided on a surface of the semiconductor chip,control terminals (e.g., gate electrodes) and first terminals (e.g.,drain electrodes) are alternately provided in the same direction.Therefore, the direction of extracting the output of the firstamplifying stage (the extending direction of the wire) and the directionof extracting the output of the second amplifying stage (the extendingdirection of the wire) are not close and adjacent to each other, whichmakes it possible to prevent any reduction in the gain and isolationattributable to a mutual induction effect between the wires.

[0037] (d) Since the input wire connected to the control terminal of thesecond amplifying stage provided on the surface of the semiconductorchip and the output wire connected to the first terminal of the secondamplifying stage extend in directions orthogonal to each other or indirections crossing each other, it is possible to suppress crosstalkbetween them.

[0038] (e) A predetermined bias resistance ratio can be achieved bysetting a bonding program for the threshold voltage Vth of eachtransistor and by connecting predetermined bias resistors with theelectrical connectors (bonding wires) based on the set program (there isan alternative of providing no connection with the electricalconnectors). The resistance of a bias resistor constituted by aconductive layer formed on a semiconductor chip can be defined withaccuracy of 5 % or less. It is therefore possible to set an optimum biaspotential for each transistor to stabilize the operating point of thetransistor. As a result, variations of a power control curve (Vapc-Pout)can be reduced to provide improved characteristics.

[0039] (f) A wireless communication apparatus incorporating a highfrequency power amplifier having the advantages described in the above(a) through (e) is capable of high performance dual band communicationand can be provided at a low cost with a compact size.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040]FIG. 1 is a schematic diagram showing a method of adjusting biasresistance ratios in accordance with a threshold voltage Vth of atransistor in a high frequency power amplifier which is an embodiment(first embodiment) of the invention.

[0041]FIG. 2 is a schematic sectional view of a part of a semiconductorchip on which the above-described adjustment of bias resistance ratioshas been completed.

[0042]FIG. 3 is a plan view of the high frequency power amplifier of thefirst embodiment.

[0043]FIG. 4 is a side view of the high frequency power amplifier of thefirst embodiment.

[0044]FIG. 5 is a front view of the high frequency power amplifier ofthe first embodiment.

[0045]FIG. 6 is a schematic perspective plan view showing a pattern ofelectrodes on a bottom surface of the high frequency power amplifier ofthe first embodiment.

[0046]FIG. 7 is an equivalent circuit diagram of the high frequencypower amplifier of the first embodiment.

[0047]FIG. 8 is a flow chart showing a part of the fabrication of thehigh frequency power amplifier of the first embodiment.

[0048]FIG. 9 is a schematic plan view of semiconductor chipsincorporated in the high frequency power amplifier of the firstembodiment.

[0049]FIG. 10 is a graph showing current-voltage characteristics of atransistor.

[0050]FIG. 11 is a table for selection of modes of ball bonding foradjusting a bias resistance ratio of a transistor incorporated in thehigh frequency power amplifier of the first embodiment.

[0051]FIG. 12 is a schematic plan view of semiconductor chips on whichthe above-described adjustment of a bias resistance ratio has beencompleted.

[0052]FIG. 13 is a plan view showing wirings provided between electrodesof the semiconductor chips incorporated in the high frequency poweramplifier of the first embodiment and wire bonding pads.

[0053]FIGS. 14A and 14B are plan views showing wirings provided betweenelectrodes of the semiconductor chips incorporated in the high frequencypower amplifier of the first embodiment and wire bonding pads and otherwirings.

[0054]FIG. 15 is a block diagram of a part of a wireless communicationapparatus incorporating the high frequency power amplifier of the firstembodiment showing a functional configuration of the same.

[0055]FIG. 16 is a sectional view of an HBT incorporated in the highfrequency power amplifier of the first embodiment.

[0056]FIG. 17 is a sectional view of the HBT incorporated in the highfrequency power amplifier of the first embodiment taken on another planeof the same.

[0057]FIG. 18 is a sectional view of a Si-GeFET incorporated in the highfrequency power amplifier of the first embodiment.

[0058]FIG. 19 is an equivalent circuit diagram of a high frequency poweramplifier which is another embodiment of the invention (secondembodiment).

[0059]FIG. 20 is a circuit diagram illustrating control of biasresistance utilizing an operational amplifier in the second embodiment.

[0060]FIG. 21 is a schematic sectional view of semiconductor chipsincorporated in the high frequency power amplifier of the secondembodiment.

[0061]FIG. 22 is a flow chart showing a part of processes of thefabrication of a semiconductor chip incorporated in the high frequencypower amplifier of the second embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0062] Preferred embodiments of the invention will now be described indetail with reference to the accompanying drawings. Throughout thedrawings for illustrating preferred embodiments of the invention, partshaving like functions are indicated by like reference numbers andrepetition will be avoided in describing them.

[0063] [First Embodiment]

[0064] The first embodiment will refer to a high frequency poweramplifier having an amplifying system for GSM and an amplifying systemfor DCS and to an example of an application of the invention to awireless communication apparatus incorporating such a high frequencypower amplifier.

[0065] As shown in the plan view in FIG. 3, the side view in FIG. 4, andthe front view in FIG. 5, a high frequency power amplifier (highfrequency power amplifier module) 20 has a flat rectangular structure inits external appearance. FIG. 6 is a schematic perspective plan viewshowing a pattern of electrodes on a bottom surface of the highfrequency power amplifier.

[0066] The high frequency power amplifier 20 is constructed in the formof a package 23 with a flat rectangular structure consisting of a modulesubstrate 21 constituted by a plate-like wiring substrate and a cap 22mounted on one surface (principal surface) of the module substrate 21 inan overlapping relationship. The cap 22 is made of a metal whichprovides an electromagnetic shielding effect. A circuit as shown in FIG.7 is formed by a wiring pattern on the module substrate 21 andsemiconductor amplification devices loaded on the module substrate 21.

[0067] As shown in FIG. 3 and FIG. 6, external electrode terminals areprovided across a circumferential surface and a bottom surface of thehigh frequency power amplifier 20. The external electrode terminals aresurface mount type terminals which are formed by wirings formed on themodule substrate 21 and solder provided on the surface of the wirings.Reference numerals 1, 2, 7, and 8 represent non-contact terminals N/C;reference numeral 3 represents a terminal for Pout-DCS; referencenumeral 4 represents a terminal for Vdd-DCS; reference numeral 5represents a terminal for Vdd-GSM; reference numeral 6 represents aterminal for Pout-GSM; reference numeral 9 represents a terminal forPin-GSM; reference numeral 10 represents a terminal for Vapc-GSM;reference numeral 11 represents a terminal for Vapc-DCS; referencenumeral 12 represents a terminal for Pin-DCS; and reference symbol Grepresents a ground terminal.

[0068] As shown in FIG. 7, the high frequency power amplifier has anamplifying system e for GSM and an amplifying system f for DCS. Theamplifying systems e and f have the same circuit configuration, althoughthere are differences in performance between some electronic componentsused in those systems. Therefore, when describing the amplifying systeme, the reference numbers of components in the amplifying system fcorresponding to those in the amplifying system e are shown in bracketsto indicate that the description also applies to the amplifying systemf.

[0069] The external electrode terminals of the amplifying system e arePin-GSM (Pin-DCS in the amplifying system f) as an input terminal,Pout-GSM (Pout-DCS in the amplifying system f) as an output terminal,Vdd-GSM (Vdd-DCS in the amplifying system f) as a first referencepotential (power supply potential), and Vapc-GSM (Vapc-DCS in theamplifying system f) as a bias terminal. A ground terminal is providedas a second reference potential.

[0070] Three amplifying stages are cascaded between the terminalsPin-GSM (Pin-DCS) and Pout-GSM (Pout-DCS). The first, second, and thirdamplifying stages are constituted by transistors Q1, Q2, and Q3 (Q4, Q5,and Q6), respectively.

[0071] Each of the transistors serving as an amplifying stage iscomprised of a control terminal (gate electrode) for receiving an inputsignal and a bias potential supplied to the stage, a first terminal(drain electrode) for transmitting an output signal from the stage, anda second terminal (source electrode) for receiving a reference potential(ground potential) for the stage.

[0072] The terminal Pin-GSM (Pin-DCS) is connected to the gate electrodeof the transistor Q1 (Q4) through a matching circuit L1 (L8). Since theamplifying system has a three-stage configuration, the gate electrodesof the transistors of the second and third stages are both connected tothe drain electrodes of the transistor of the preceding stages throughmatching circuits L3 (L10) and L5 (L12). The drain electrode of thetransistor Q3 (Q6) that is an output stage or a final amplifying stageis connected to the terminal Pout-GSM (Pout-DCS) through a matchingcircuit L7 (L14).

[0073] The drain electrodes of the transistors Q1, Q2, and Q3 areconnected to the terminal Vdd-GSM (Vdd-DCS) through matching circuitsL2, L4, and L6 (L9, L11, and L13).

[0074] The gate electrodes of the transistors Q1, Q2, and Q3 areconnected to the terminal Vapc-GSM (Vapc-DCS). Bias circuits areprovided between the gate electrodes and the terminal Vapc-GSM(Vapc-DCS) to control bias potentials to be applied to the respectivegate electrodes. The bias circuits are constituted by bias resistors R1through R5 (R6 through R10) that provide voltage dividing resistance.

[0075] The part indicated by the box in a broken line in FIG. 7 is asemiconductor chip (FET chip) 25. The semiconductor chip 25monolithically incorporates the transistors Q1 and Q2 of the amplifyingsystem e for GSM, the bias resistors R1, R2, R3, R4, and R5 thatdetermine bias resistance ratios for the transistors Q1 and Q2, thetransistors Q4 and Q5 of the amplifying system f for DCS, and the biasresistors R6, R7, RB, R9, and R10 that determine bias resistance ratiosfor the transistors Q4 and Q5. This makes it possible to reduce thenumber of components, thereby allowing a reduction in the size andmanufacturing cost of the high frequency power amplifier.

[0076] One of the features of the invention is that the first embodimenthas a configuration in which the bias resistance ratios can be changedduring assembly in accordance with variations of threshold voltages Vthof the transistors. Specifically, FIG. 1 is a schematic diagram showingan example of an application of the invention to the region the biascircuit of the transistor Q1. The part enclosed in the box in a dottedline is a bias resistance ratio correcting section. In the biasresistance ratio correcting section, five bonding portions Wpa, Wpb,Wpc, Wpd, and Wpe are provided in series in a state in which they areelectrically isolated from each other. The bonding portions areconstituted by a conductive layer and are formed on a surface of thesemiconductor chip 25. The bonding portions Wpa, Wpb, Wpc, and Wpd arein a programmable configuration in which only adjoining bonding portionscan be electrically connected by securing an electrical connector 40constituted by a conductor between the adjoining bonding portions. InFIG. 1, connecting positions are indicated by (a), (b), and (c). In FIG.1, for example, an electrical connector 40 is secured at the connectingposition (a) (see FIG. 2) to electrically connect the bonding portionsWpc and Wpd. Resistive elements R3-1, R3-2, and R3-3 are provided on aside of the bonding portions Wpa, Wpb, Wpc, Wpd, and Wpe.

[0077] The bonding portions Wpa, Wpb, Wpc, Wpd, and Wpe and theresistive elements R3-1, R3-2, and R3-3 are connected as described belowthrough wirings to which no reference symbol is assigned. The terminalVapc (Vapc-GSM) is connected to the bonding portion Wpb through a wire,and the bonding portion Wpe is connected to the bias resistor R2 througha wire. One end of the resistive element R3-3 is connected to thebonding portion Wpb through a wire, and the other end of the same isconnected to the bonding portion Wpc through a wire. One end of theresistive element R3-2 is connected to the bonding portion Wpc through awire, and the other end of the same is connected to the bonding portionWpd through a wire. The bonding portion Wpa and the bonding portion Wpdare connected through a separate wire. One end of the resistive elementR3-1 is connected to the bonding portion Wpd through a wire, and theother end of the same is connected to the bonding portion Wpe through awire.

[0078] Therefore, the adjustment of the bias resistance ratio can becarried out in four modes (a) through (d) as shown in FIG. 1. Referringto FIG. 1, in a connection mode (a), the electrical connector is securedto a connecting position (a), which results in a bias resistance ratioof R1/[R1+R2+(R3-1)]. In a connection mode (b), the electrical connectoris secured to a connecting position (b), which results in a biasresistance ratio of R1/[R1+R2+(R3-1)+(R3-2)]. In a connection mode (c),the electrical connector is secured to a connecting position (c), whichresults in a bias resistance ratio of

[0079] R1/[R1+R2+(R3-1)+(R3-3)]. In a connection mode (d), theelectrical connector is not bonded, which results in a bias resistanceratio of R1/[R1+R2+(R3-1)+(R3-2)+(R3-3)].

[0080] The connection of the electrical connector 40 will now bedescribed. FIG. 8 is a flow chart showing processing steps (S) of a partof the fabrication of a high frequency power amplifier, i.e., a flowchart showing steps starting from a probe inspection (S311) that isfollowed by dicing/chip screening (S312), chip mounting (S313), andselection of resistors (S314).

[0081] After forming semiconductor devices in longitudinal and lateraldirections on a surface of a semiconductor substrate which is not shown,the characteristics of the semiconductor devices are inspected (probeinspection); the semiconductor substrate is then cut in the longitudinaland lateral directions (dicing); and only semiconductor devices(semiconductor chips) judged to be good at the probe inspection areused.

[0082] Next, the semiconductor chips are mounted to predeterminedpositions of the above-described module substrate 21, and positions tosecure the electrical connectors 40 are selected in accordance with thethreshold voltages Vth of the transistors of the semiconductor chips. Inthis example, as shown in FIG. 12, the bias resistance ratios of thetransistor Q1 of the GSM amplifying system e and the transistor Q4 ofthe DCS amplifying system f can be adjusted.

[0083] As shown in the graph in FIG. 10, slight deviations (ΔVth) of thethreshold voltage Vth of transistors occur between production lots. Inorder to solve this, as shown in FIG. 11, four modes of connection areemployed depending on values of the threshold voltage Vth to obtain apredetermined bias resistance ratio. Specifically, when the thresholdvoltage Vth is a value within ranges (1) and (2), the position (a) shownin FIG. 1 is selected as the connection position. Similarly, theposition (b) shown in FIG. 1 is selected as the connecting position whenthe threshold voltage Vth is within ranges (3) and (4), and the position(c) shown in FIG. 1 is selected as the connecting position when thethreshold voltage Vth is within ranges (5) and (6). The electricalconnector is connected to nowhere when the threshold voltage Vth iswithin ranges (7) and (8) as shown in the mode (d). Although no specificvalue is shown for the ranges (1), (2), and so on, an appropriate valuemay be selected for each range. FIG. 2 shows a state in which theelectrical connector 40 is connected to the position (a). The electricalconnector 40 is provided by cutting a wire in the vicinity of a ballportion of the same after nail head bonding.

[0084] The bias resistance ratio can be corrected by selecting theposition of the electrical connector appropriately or making noconnection, which makes it possible to compensate the threshold voltageVth of the transistors Q1 and Q4 for any variation. The adjustment ofthe bias resistance ratio may be performed on the transistor of thesecond amplifying stage, although not performed on the final amplifyingstage.

[0085]FIG. 9 is a plan view schematically showing the semiconductor chip25. Similarly to FIG. 12, FIG. 9 shows the gate electrodes (G) and drainelectrodes (D) of the first stage transistors (first FETS) and secondstage transistors (second FETS) for GSM and DCS. FIG. 9 omits some partsof the chip to avoid complicatedness, and no reference numeral is shownfor each part of a bias resistance ratio correcting section.

[0086] It is one of the features of the invention that the gateelectrodes (G) and drain electrodes (D) of the first EFTs and secondFETs are laid out such that they are alternately provided in the samedirection. In such a layout, the direction of extracting the output ofthe first FETs (first amplifying stage) or the direction in which wiresextend therefrom is not close and adjacent to the direction ofextracting the output of the second FETs (second amplifying stage) orthe direction in which wires extend therefrom (see FIG. 13), which makesit possible to present any reduction in gain and isolation attributableto a mutual induction effect between the wires. That is, any reductionin isolation can be suppressed, and any reduction in gain attributableto a mutual induction effect between the wires can be prevented.

[0087] It is another feature of the invention that wires 41 connected tothe gate electrodes of the second FET (Q2) of the GMS amplifying systemand the second FET (Q5) of the DCS amplifying system extend in anorthogonal relationship with wires 41 connected to the drain electrodesof the same, as shown in FIG. 13 and FIG. 14A. This makes it possible toprevent crosstalk between input power and output power. Crosstalk can beprevented by setting the wires in a crossed state that is similar to anorthogonal relationship instead of setting them in an orthogonalrelationship. Other ends of the wires 41 are connected to wire bondingpads 42 provided in a part of the wiring.

[0088] As shown in FIG. 9, the transistor (first FET) Q1 of the firstamplifying stage and the transistor (second FET) Q2 of the secondamplifying stage of the semiconductor chip in the first embodiment areprovided in the same direction. This suppresses variation of electricalcharacteristics (Vth versus drain current characteristics).Specifically, when the source-drain directions of the first and secondFETs in which current flows are orthogonal to each other, the crystalaxis of the semiconductor substrate is changed by 90 deg., whichincreases the possibility of variation of characteristics during a heattreatment.

[0089] As shown in FIG. 14B, when the first and second FETs for GSM areincorporated in a single semiconductor chip and the first and secondFETs for DCS are incorporated in a single semiconductor chip, aconfiguration may be employed in which ground wiring is provided betweenthe first and second FETs to prevent any reduction in the gainattributable to a mutual induction effect between the wires. However,such a configuration can not be used as it is in the present embodimentin which the two amplifying systems are incorporated in a singlesemiconductor chip. Therefore, the present embodiment has theconfiguration shown in FIG. 14A.

[0090] As shown in FIG. 15, such a high frequency power amplifier isused by incorporating the same in a wireless communication apparatus.FIG. 15 is a block diagram of a part of a dual band wirelesscommunication apparatus showing a part of the same ranging from a highfrequency signal processing IC (RF linear) 50 to an antenna 51. FIG. 15shows two separate amplifiers as the amplifying system of the highfrequency power amplifier, i.e., an amplifying system for GSM and anamplifying system for DCS, the amplifiers being represented by PA (poweramplifier) 20 a and 20 b.

[0091] The antenna 51 is connected to an antenna terminal Antenna of anantenna transmission/reception switch 52. The antennatransmission/reception switch 52 has terminals Pout 1 and Pout 2 towhich the output of the amplifiers PA 20 a and 20 b is input, receptionterminals RX1 and RX2, and control terminals control 1 and control 2.

[0092] A GSM signal from the high frequency signal processing IC 50 istransmitted to the amplifier PA 20 a and output to the terminal Pout 1.The output of the amplifier PA 20 a is detected by a coupler 54 a, andthe detection signal is fed back to an automatic power control circuit(APC circuit) 53. The APC circuit 53 operates based on the detectionsignal to control the amplifier PA 20 a.

[0093] Similarly, a DCS signal from the high frequency signal processingIC 50 is transmitted to the amplifier PA 20 b and output to the terminalPout 2. The output of the amplifier PA 20 b is detected by a coupler 54b, and the detection signal is fed back to the APC circuit 53. The APCcircuit 53 operates based on the detection signal to control theamplifier PA 20 b.

[0094] The antenna transmission/reception switch 52 has a duplexer 55.The duplexer 55 has three terminals. One of the terminals is connectedto the antenna terminal Antenna. One of the remaining two terminals isconnected to a transmission/reception select switch 56 a for GSM, andthe other is connected to a transmission/reception select switch 56 bfor DCS.

[0095] An a-contact of the transmission/reception select switch 56 a isconnected to the terminal Pout 1 through a filter 57 a. A b-contact ofthe transmission/reception select switch 56 a is connected to thereception terminal RX1 through a capacity C1. At thetransmission/reception select switch 56 a, switching is performed basedon a control signal input to the control terminal control 1 to establishelectrical connection to the a-contact or b-contact.

[0096] An a-contact of the transmission/reception select switch 56 b isconnected to the terminal Pout 2 through a filter 57 b. A b-contact ofthe transmission/reception select switch 56 b is connected to thereception terminal RX2 through a capacity C2. At thetransmission/reception select switch 56 b, switching is performed basedon a control signal input to the control terminal control 2 to establishelectrical connection to the a-contact or b-contact.

[0097] A filter 60 a and a low noise amplifier (LNA) 61 a aresequentially connected between the reception terminal RX1 and highfrequency signal processing IC 50. A filter 60 b and a low noiseamplifier (LNA) 61 b are sequentially connected between the receptionterminal RX2 and high frequency signal processing IC 50.

[0098] Such a wireless communication apparatus is capable of GSMcommunication and DCS communication.

[0099] The first embodiment has the following advantages.

[0100] (1) Since the first amplifying stage (transistors Q1 and Q4) forthe GSM amplifying system e and DCS amplifying system f aremonolithically formed on the single semiconductor chip 25, a smallersize can be achieved compared to a structure in which they areincorporated in separate semiconductor chips. Since a part of biasresistors that constitute bias circuits for the first and secondamplifying stages are monolithically formed on the semiconductor chip25, the high frequency power amplifier can be made compact compared to astructure in which the chip resistors are separately mounted.

[0101] (2) The size and manufacturing cost of the high frequency poweramplifier can be reduced through a reduction in the number of componentsthat is achieved by monolithically forming the first amplifying stagesand second amplifying stages of the GSM amplifying system e and the DCSamplifying system f on the single semiconductor chip 25 and bymonolithically forming a part of the bias resistors that constitute thebias circuits for the first amplifying stage and second amplifying stageon the semiconductor chip 25 as described in the above (1).

[0102] (3) Referring to the terminals of the first amplifying stage andsecond amplifying stage provided on a surface of the semiconductor chip25, the control terminals (e.g., gate electrodes) and first terminals(e.g., drain electrodes) are alternately provided in the same direction.Therefore, the direction of extracting the output of the firstamplifying stage (the extending direction of the wire) and the directionof extracting the output of the second amplifying stage (the extendingdirection of the wire) are not close and adjacent to each other, whichmakes it possible to prevent any reduction in the gain and isolationattributable to a mutual induction effect between the wires 41.

[0103] (4) Since the input wire 41 connected to the control terminal ofthe second amplifying stage provided on the surface of the semiconductorchip 25 and the output wire 41 connected to the first terminal of thesecond amplifying stage extend in directions orthogonal to each other orin directions crossing each other, it is possible to suppress crosstalkbetween them.

[0104] (5) A Predetermined bias resistance ratio can be achieved bysetting a bonding program for the threshold voltage Vth of eachtransistor and by connecting predetermined bias resistors with theelectrical connectors (bonding wires) 40 based on the set program (thereis an alternative of providing no connection with the electricalconnectors). The resistance of a bias resistor constituted by aconductive layer formed on a semiconductor chip 25 can be defined withaccuracy of 5 % or less. It is therefore possible to set an optimum biaspotential for each transistor to stabilize the operating point of thetransistor. As a result, variations of a power control curve (Vapc-Pout)can be reduced to provide improved characteristics.

[0105] (6) A wireless communication apparatus incorporating a highfrequency power amplifier having the advantages described in the above(1) through (5) is capable of high performance dual band communicationand can be provided at a low cost with a compact size.

[0106] While the first embodiment has referred to an example in whichMOS (metal oxide conductor) FETs are used as semiconductor amplifyingelements that constitute amplifying stages, other transistors may beused. For example, the transistors may be silicon bipolar transistors,GaAs-MES (metal semiconductor) FETs, HBTs (hetero-junction bipolartransistors), HEMTs (high electron mobility transistors), Si-GeFETs orthe like. The use of transistors with high performance will beadvantageous especially in the final amplifying stage that serves as anoutput stage. HBTs and Si-GeFETs will now be briefly described.

[0107] Each of FIG. 16 and FIG. 17 is a sectional view of an HBT. Ann⁺-type GaAs sub-collector layer 66 is provided on a semi-insulatingGaAs substrate 65, and an n-type GaAs collector layer 67 is provided onthe n⁺-type GaAs sub-collector layer 66. The n-type GaAs sub-collectorlayer 67 is selectively etched halfway to form a mesa portion thatprotrudes in a part of the same layer. In a region which is off the mesaportion and in which the thin n-type GaAs sub-collector layer 67 isformed, the n-type GaAs sub-collector layer 67 is partially etched, anda collector electrode 75 is provided in the etched region.

[0108] A p⁺-type GaAs base layer 68, an n-type InGaP emitter layer 69,and an n⁺-type GaAs cap layer 70 are sequentially formed on the mesaportion in an overlapping relationship. While the p⁺-type GaAs baselayer 68 and n-type InGaP emitter layer 69 are in substantially the samesize and are overlapped in alignment with each other, the n⁺-type GaAscap layer 70 is formed in the middle of the mesa portion in a narrowrectangular configuration.

[0109] The n-type InGaP emitter layer 69 and n⁺-type GaAs cap layer 70are selectively etched in a mesa region out of the n⁺-type GaAs caplayer 70 to provide a contact hole, and a base electrode 71 is providedin the contact hole.

[0110] The top surface of the semi-insulating GaAs substrate 65 iscovered by an insulation film 72 for surface protection. The insulationfilm 72 is partially etched to form contact holes that provideelectrical contact of each electrode of the HBT. Before forming theabove-described top insulation film, an emitter electrode 73 (two layersare shown in FIG. 16) is formed on the n⁺-type GaAs cap layer 70. Then,wiring metals 74 are formed after forming contact holes, and the wiringmetals 74 are connected to the emitter electrode 73, base electrode 71,and collector electrode 75.

[0111] During the fabrication of the HBT, etching is performed to forman isolation groove 76 in the n-type GaAs collector layer 67 and n⁺-typeGaAs sub-collector layer 66. The isolation groove 76 reaches the top ofthe semi-insulating GaAs substrate 65. A metal layer 77 is provided onthe bottom of the isolation groove 76 as an etching stopper. A contacthole 78 is provided on the bottom surface of the semi-insulatingsubstrate 65. The hole 78 is formed such that its bottom is defined bythe meta; layer 77. The wiring metals 74 are electrically connected tothe metal layer 77 through conduction wiring 79 filled in holes providedin the insulation film 72. An electrode 80 is also provided on thebottom surface of the semi-insulating GaAs substrate 65, and theelectrode 80 is connected to the emitter electrode 73 through the metallayer 77 and conduction wiring 79. Reference numeral 81 in the figurerepresents a resistor.

[0112]FIG. 18 is a schematic sectional view of a Si-GeFET. As shown inFIG. 1, a Si-GeFET 100 has a structure in which a SiGe distortionimparting layer 102 made of Si_(1-x)Ge_(x) (0≦X≦1) and a distorted Sichannel layer 104 are sequentially formed and grown on a top surface(principal surface) of a Si substrate 101. It also has a structure inwhich a SiO₂ insulation layer 103 is provided in the Si substrate 101near the surface thereof.

[0113] In the Si layer above the distorted Si channel layer 104, SiGedistortion imparting layer 102, and SiO₂ insulation layer 103, a deviceseparating insulation region 105 is formed which penetrates to reach theSiO₂ insulation layer 103 at the bottom thereof. A pair of diffusionregions 108 to serve as a source region and drain region of a fieldeffect transistor are provided in a device forming region 121 surroundedby the device separating insulation region 105.

[0114] A gate oxide film 106 is provided on the surface of the distortedSi channel layer 104 between the pair of diffusion regions 108. A gateelectrode 107 is provided on the gate oxide film 106, and sidewalls 122constituted by an insulator are provided on both ends of the gate oxidefilm 106 and gate electrode 107. The diffusion region 108 is provided onboth sides of the gate oxide film 106.

[0115] A layer insulation film 109 is provided on the distorted Sichannel layer 104, gate electrode 107, and sidewalls 122. Contact holesare provided in the layer insulation film 109, and metal wiring 111 isformed in the contact holes to form gate wiring connected to the gateelectrode 107 and source and drain wiring connected to the diffusionregion 108, thereby providing a field effect transistor.

[0116] [Second Embodiment]

[0117]FIG. 19 is a circuit diagram of a high frequency power amplifierwhich is another embodiment (second embodiment) of the invention. In thepresent embodiment, the above-described first embodiment is modifiedsuch that a bias control circuit 85 is incorporated in the semiconductorchip 25 and such that output signals from the bias control circuit 85are respectively output to operational amplifiers Opamp 1 through Opamp6 to control the bias resistance of the transistors Q1 through Q6.

[0118]FIG. 20 is a circuit diagram for explaining the control of biasresistance performed by the operational amplifiers.

[0119] The bias control circuit 85 outputs bias control signals for thetransistors to the operational amplifiers in accordance with a signalinput from the APC. The operational amplifiers are configured to serveas voltage followers. As shown in the example of configuration in FIG.20, the operational amplifier comprises a differential amplifierconstituted by a pair of nMOS transistors NM1 and NM2, a current mirror(also referred to as “active load circuit”) constituted by a pair ofpMOS transistors PM1 and PM2, and a source follower constituted by apMOS transistor PM3, an input voltage Vin and an output voltage Vout ofthe operational amplifier being the same voltage.

[0120]FIG. 21 is a schematic sectional view of the semiconductor chip25. As shown in FIG. 21, p-type epitaxial layers 87 are formed on onesurface of a p⁺-type silicon substrate 86. Each of the epitaxial layers87 is surrounded by a p⁺-type isolation region 88. Well regions andimpurity regions are formed in the expitaxial layer 87 electricallyisolated by the isolation region 88; gate insulation films and gateelectrodes are formed in predetermined positions; and a CMOS(complementary metal oxide semiconductor) constituted by a PMOS andNMOS, an LD (lateral double diffused) MOS, a resistor R, a protectivediode, and a PN diode are formed.

[0121] A description will be made on such a semiconductor device withreference to the flow chart in FIG. 22. The flow charts shows steps fromthe formation of LOCOS up to the formation of wiring.

[0122] After providing the p⁺-type silicon substrate 86 having theepitaxial layer 87 on one surface thereof, a LOCOS (Local Oxidation ofSilicon) film 89 is formed on the epitaxial layer 87 (S401).

[0123] A resistive layer 90 is then formed in a part of the LOCOS film89 (S402). Next, a predetermined impurity is implanted in the epitaxiallayer 87 to form the isolation region 88 and well regions. Specifically,an n-type well NW1 is formed in the location where the protective diodeis to be formed; n-type wells NW2 are formed in the locations where thePMOS and PN diode are to be formed; and p-type wells PW are formed inthe locations where the NMOS and LDMOS are to be formed (S403 throughS405).

[0124] Gate regions are then formed (S406). Specifically, gateinsulation films 92 constituted by thermal oxidation films are formed inthe locations where the LDMOS, PMOS, and NMOS are to be formed, and gateelectrodes 93 made of polysilicon are formed on the gate insulationfilms 92 in an aligned and overlapping relationship.

[0125] Next, a normal photolithographic technique and impurity diffusingtechnique are used to sequentially and selectively diffuse an impurityto form p⁺regions, n⁺regions, and n⁻regions, thereby formingsemiconductor regions to serve as FETs and semiconductor regions toserve as diodes.

[0126] Next, a layer insulation film 94 is formed on the entrire surface(S408). Thereafter, contact holes are formed in the layer insulationfilm 94 (S409). The contact holes are formed such that they extendtoward predetermined p⁺regions and n⁺regions, and the p⁺regions andn⁺regions are exposed at the bottom of the contact holes.

[0127] Next, wires 95 are formed. The wires 95 are indicated by dots.The wires 95 are filled in the contact holes to be connected to therespective p⁺regions and n⁺regions. Thereafter, for example,planarization is carried out; an insulation film and wires are furtherformed; and a final passivation film is finally formed. While thep⁺-type silicon substrate 86 has been described with reference to anillustration that shows only a region where a single semiconductor chipis formed, a semiconductor substrate having a large diameter is used inpractice and is finally cut in longitudinal and lateral directions intoindividual semiconductor chips, thereby forming a multiplicity ofsemiconductor chips.

[0128] LDMOSs, resistors R, protective diodes, PMOSs, PN diodes, andNMOSs are thus formed. The PMOSs and NMOSs form CMOSs of the operationalamplifiers, and LDMOSs form the transistors Q1 through Q6.

[0129] The high frequency power amplifier of the present embodiment isadvantageous in that it has a reduced surface area and improved powerefficiency compared in addition to the advantages provided by the highfrequency power amplifier of the first embodiment.

[0130] While the invention conceived by the inventors has beenspecifically described with reference to preferred embodiments of thesame, the invention is not limited to the above-described embodiments,and various modifications are obviously possible within the scope of theprinciple of the invention. Specifically, the embodiments have referredto a technique for connecting predetermined portions with an electricalconnector as a feature for adjusting a bias resistance ratio, a methodmay alternatively employed in which a plurality of wiring sections areselectively cut through laser trimming to adjust a bias resistanceratio. Further, while the embodiments have referred to dual bandsystems, the invention may be similarly applied to multi-modecommunication systems and multi-band and multi-mode communicationsystems with similar advantages.

[0131] Advantages provided in primary aspects of the invention disclosedin the present specification can be summarized as follows.

[0132] (1) A reduction in the number of components can be achieved bymonolithically forming first and second amplifying stages of eachamplifying system on a single semiconductor chip and by monolithicallyforming a part of bias resistors that constitute bias circuits for thefirst and second amplifying stages on the semiconductor chip.

[0133] (2) The size and manufacturing cost of a high frequency poweramplifier can be achieved through a reduction in the number ofcomponents as described in the above (1). (3) Any reduction in gain andisolation attributable to a mutual induction effect between wires can beprevented by providing terminals of the first and second amplifyingstages on the surface of the semiconductor chip in specific locations.

[0134] (4) Since the input wire connected to the control terminal of thesecond amplifying stage provided on the surface of the semiconductorchip and the output wire connected to the first terminal of the secondamplifying stage extend in directions orthogonal to each other or indirections crossing each other, it is possible to suppress crosstalkbetween them.

[0135] (5) A predetermined bias resistance ratio can be achieved bysetting a bonding program for the threshold voltage Vth of eachtransistor and by connecting predetermined bias resistors with theelectrical connectors (bonding wires) based on the set program (there isan alternative of providing no connection with the electricalconnectors). As a result, the resistance of a bias resistor constitutedby a conductive layer formed on a semiconductor chip can be defined withaccuracy of 5 % or less. It is therefore possible to set an optimum biaspotential for each transistor to stabilize the operating point of thetransistor and to provide improved characteristics.

[0136] (6) A wireless communication apparatus incorporating a highfrequency power amplifier having the advantages described in the above(1) through (5) is capable of high performance dual band communicationand can be provided at a low cost with a compact size.

What is claimed is:
 1. A high frequency power amplifier having aplurality of amplifying systems, each of said amplifying systemscomprising: an input terminal to which a signal to be amplified issupplied; an output terminal; a bias terminal; a plurality of amplifyingstages which are sequentially cascaded between said input terminal andoutput terminal; and a bias circuit connected to said bias terminal andeach of said amplifying stages to apply a bias potential to saidamplifying stage, said amplifying stage including a control terminal forreceiving an input signal and said bias potential supplied to the stageand a first terminal for transmitting an output signal of the stage, afirst amplifying systems and a second amplifying stage of each of saidamplifying stages being monolithically formed on a single semiconductorchip, a part of bias resistors included in the bias circuits of saidfirst amplifying stage and second amplifying stage being monolithicallyformed on said semiconductor chip.
 2. A high frequency power amplifieraccording to claim 1, wherein said control terminals and first terminalsof said first amplifying stage and second amplifying stage on a surfaceof said semiconductor chip are alternately provided in the samedirection.
 3. A high frequency power amplifier according to claim 1,wherein a wire that is connected to the control terminal of said secondamplifying stage provided on a surface of said semiconductor chip and awire connected to the first terminal of said second amplifying stageextend in directions crossing each other.
 4. A high frequency poweramplifier according to claim 3, wherein the wire that is connected tothe control terminal of said second amplifying stage and the wireconnected to the first terminal of said second amplifying stage extendin directions orthogonal to each other.
 5. A high frequency poweramplifier according to claim 1, wherein a bias resistance ratio of thefirst amplifying stage of each of said amplifying stages or biasresistance ratios of the first amplifying systems and second amplifyingstage can be adjusted.
 6. A high frequency power amplifier according toclaim 5, wherein the bias resistance ratio of the first amplifying stageof each of said amplifying systems or the bias resistance ratios of thefirst amplifying stage and second amplifying stage are adjusted byselecting connecting positions of electrical connectors that connect theplurality of bias resistors formed on the surface of said semiconductorchip, the choice including no connection with the electrical connectors.7. A high frequency power amplifier according to claim 1, wherein a biascontrol circuit is connected to said bias terminal and wherein terminalsof the bias control circuit for output to said first amplifying stageand second amplifying stage are connected to the control terminals ofsaid first amplifying stage and second amplifying stage.
 8. A highfrequency power amplifier according to claim 1, wherein a transistorthat serves as the final amplifying stage of each of said amplifyingsystems is any of a Si-MOSFET, SiGe-FET, GaAs-MESFET, HEMT, andhetero-junction type bipolar transistor.
 9. A wireless communicationapparatus comprising a high frequency power amplifier according toclaim
 1. 10. A high frequency power amplifier according to claim 1,wherein a transistor included in each of said plurality of amplifyingstages is an FET of a first conductivity type and wherein an FET of thefirst conductivity type and an FET of a second conductivity type areformed on said semiconductor chip.
 11. A high frequency power amplifierhaving a plurality of amplifying systems, said amplifying systemcomprising: an input terminal to which a signal to be amplified issupplied; an output terminal; a bias terminal; a plurality of amplifyingstages which are sequentially cascaded between said input terminal andoutput terminal; and a bias circuit connected to said bias terminal andeach of said amplifying stages to apply a bias potential to saidamplifying stage, said amplifying stage including a control terminal forreceiving an input signal and said bias potential supplied to the stageand a first terminal for transmitting an output signal of the stage, afirst amplifying stage and a second amplifying stage of said amplifyingstage being monolithically formed on a single semiconductor chip, a partof bias resistors included in the bias circuits of said first amplifyingstage and second amplifying system being monolithically formed on saidsemiconductor chip, the bias resistance ration of the first amplifyingstage of said amplifying system or the bias resistance ratios of thefirst amplifying stage and second amplifying stage being adjustable. 12.A high frequency power amplifier according to claim 11, wherein the biasresistance ratio of the first amplifying stage of said amplifying systemor the bias resistance ratios of the first amplifying stage and secondamplifying stage are adjusted by selecting connecting positions ofelectrical connectors that connect the plurality of bias resistorsformed on the surface of said semiconductor chip, the choice includingno connection with the electrical connectors.
 13. A high frequency poweramplifier according to claim 11, wherein a transistor that serves as thefinal amplifying stage of said amplifying system is any of a Si-MOSFET,SiGe-FET, GaAs-MESFET, HEMT, and hetero-junction type bipolartransistor.
 14. A wireless communication apparatus comprising a highfrequency power amplifier according to claim 11.